1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, to a MOSFET anti-fuse.
2. Background Art
In the field of data storage, there are two main types of storage elements. The first type is volatile memory that has the information stored in a particular storage element, and the information is lost the instant the power is removed from a circuit. The second type is a nonvolatile storage element, in which the information is preserved even with the power removed. In regards to the nonvolatile storage elements, some designs allow multiple programming, while other designs allow one-time programming. Typically, the manufacturing techniques used to form nonvolatile memories are quite different from a standard logic process, which dramatically increases the complexity and chip size.
Complimentary Metal Oxide Semiconductor (CMOS) technology is the integration of both NMOS and PMOS tansistors on a silicon substrate (collectively know as MOS field effect transistors, or MOSFETs). The NMOS transistor consists of a N-type doped polysilicon gate, a channel conduction region, and source/drain regions formed by diffusion of N-type dopants in the silicon substrate. The channel region separates the source from the drain in the lateral direction, whereas a layer of dielectric material that prevents electrical current flow separates the polysilicon gate from the channel. Similarly, the architecture is the same for the PMOS transistor, except a P-type dopant is used.
The dielectric material separating the polysilicon gate from the channel region, henceforth referred to as the gate oxide, usually consists of the thermally grown silicon dioxide (SiO2) material that leaks very little current through a mechanism, which is called Fowler-Nordheim tunneling under voltage stress. When stressed beyond a critical electrical field (applied voltage divided by the thickness of the oxide), the transistor is destroyed by rupturing of the oxide.
Thin oxides that allow direct tunneling current behave quite differently than thicker oxides, which exhibit Fowler-Nordheim tunneling. Rupturing oxide requires determining an appropriate pulse width duration and amplitude to limit power through the gate oxide, which produces a reliable, low resistance anti-fuse.
What is desired is an anti-fuse structure that overcomes the variability of use resistance. Fuse resistance is much lower at edges of the source and drain regions because it is a function of breakdown spot position along the channel region. Hence, a MOSFET device without a conventional channel region is desirable to implement an anti-fuse.
Embodiments of the present invention provide an anti-fuse device that includes a substrate and source and drain regions formed in the substrate that are laterally spaced apart to form a channel between them. The anti-fuse device also includes a gate oxide formed on the channel and a gate formed on the gate oxide. The anti-fuse also includes lightly doped source and drain extension regions formed in the channel and extending across the channel from the source and the drain regions, respectively, which occupies a substantial portion of the channel. Programming of the anti-fuse is performed by application of power to the gate and at least one of the source region and the drain region to break down the gate oxide, which minimizes resistance between the gate and the channel.
In some embodiments, the power can be electrically connected to the anti-fuse device to impress a voltage on the gate, the source region, and the drain region. Also, the source and drain regions can be coupled to a same voltage or potential during programming.
In some embodiments, the source and drain regions can be heavily doped with an N type material or heavily doped with a P type material.
In some embodiments, a deep N-well region can be formed within the substrate beneath the source and drain regions and the channel, while in other embodiments a deep P-well region can be formed.
In some embodiments, the source and the drain regions can be formed in an N-well layer that is formed on the substrate, which is doped with P type material.
In some embodiments, the lightly doped source and drain extension regions can extend completely under the gate to form an overlap region within the channel.
Further embodiments, features, and advantages of the present inventions, as well as the structure and operation of the various embodiments of the present invention, are described in detail below with reference to the accompanying drawings.